1. Field
Example aspects described herein relate to determining a clock duty cycle, and more specifically for determining the duty cycle of a clock in a circuit using a configurable phase locked loop.
2. Description of Related Art
Duty cycle of a clock can be important in various circuits. For example, if digital logic is clocked on rising and falling edges of a clock, then it may be necessary to have a substantially 50-50 duty cycle. A very skewed duty cycle may not provide enough time for digital calculations before the next edge of the clock.
A common approach to measuring duty cycle of a clock is to either measure the clock with an oscilloscope or with an advanced frequency counter. Both these approaches require relatively expensive test equipment and a fair amount of labor to find the correct pin, attach or hold the probe to the pin, and analyze the data to determine if it is within limits.